Phase lock loop (PLL) type circuits “lock” on an incoming reference frequency signal and track it within the range of the PLL. If the incoming reference frequency is too low then the PLL may not be able to “lock” to the signal or if “locked” may lose “lock” if the signal frequency goes too low. Under these conditions of lost lock the output of the PLL, which is often derived from a voltage controlled oscillator (VCO) may not be stable. This presents a problem. Thus there is a great need for this technical problem to be solved by maintaining a minimum VCO frequency such that when the input signal frequency is in range to be locked that the PLL exists gracefully from the minimum VCO frequency and can resume normal operation in a closed-loop fashion.